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[https://nvbugs/6402048][test] Skip MXFP8 CUTLASS MoE with non-128-aligned per-shard intermediate - #15865

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NVIDIA:mainfrom
xxi-nv:user/xxi/waive-mxfp8-cutlass-tp-align-6402048
Jul 4, 2026
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[https://nvbugs/6402048][test] Skip MXFP8 CUTLASS MoE with non-128-aligned per-shard intermediate#15865
xxi-nv merged 2 commits into
NVIDIA:mainfrom
xxi-nv:user/xxi/waive-mxfp8-cutlass-tp-align-6402048

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@xxi-nv xxi-nv commented Jul 2, 2026

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Description

MXFP8CutlassFusedMoEMethod.create_weights hard-asserts intermediate_size_per_partition % 128 == 0 for its int32 UE8M0 scale-factor packing. When moe_tp_size > 1 shards a non-128-aligned intermediate axis — e.g. Qwen1.5-MoE-A2.7B intermediate_size=1408 with TTP/DTP moe_tp_size=4 gives per-shard 352 — the assertion raises and test_configurable_moe_multi_gpu -k "CUTLASS and FP8 and not FP8_BLOCK_SCALES and not W4A8" fails (nvbugs/6402048). The post-merge selector was matching MXFP8 via the FP8 substring even though it was intended for plain FP8 QDQ.

Changes

  1. should_skip_cutlass — add QuantAlgo.MXFP8 to tp_alignment_quants, so non-128-aligned per-shard MXFP8 configs are skipped at parameter-generation time, matching W8A16 / NVFP4 / W4A8_AWQ.
  2. waives.txt — remove the now-redundant SKIP entry (the case no longer reaches collection).
  3. l0_dgx_b200.yml post-merge — add and not MXFP8 to the CUTLASS and FP8 ... selector so it stays on plain FP8 QDQ, as its comment intends.
  4. l0_dgx_b200.yml pre-merge — add an explicit CUTLASS and MXFP8 and not W4A8 entry so aligned MXFP8 configs get real coverage.

Scope check

  • Qwen1.5-MoE (i=1408) + TTP/DTP — per-shard 352, now skipped (the failing case). EP modes (DEP/TEP, unsharded 1408) still run.
  • DeepSeek-V4 (i=2048), boundary (i=512) — all parallel modes still run (per-shard 512 / 128 aligned).
  • GPT-OSS (h/i=2880) — already skipped by the generic 128-alignment check in get_quick_skip_reason.
  • plain FP8FP8QDQFusedMoEMethod has no alignment assertion; unaffected.
  • H100 / B300 — H100 (SM90) rejects MXFP8 via can_implement (MXFP8 needs SM100/103); B300 uses detailed test-ids that don't include MXFP8. Neither needs changes.

Test Coverage

unittest/_torch/modules/moe/test_moe_module.py::test_configurable_moe_multi_gpu

  • Post-merge: plain FP8 QDQ (MXFP8 excluded).
  • Pre-merge: aligned MXFP8 CUTLASS configs now explicitly covered.

Notes

Supersedes repair-bot PR #15846 (in-kernel padding fix); this takes the lighter test-skip route consistent with the sibling non-128-aligned quant algos.

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Review Change Stack

📝 Walkthrough

Walkthrough

This PR modifies the should_skip_cutlass TP-per-shard alignment logic to include QuantAlgo.MXFP8 in the alignment quant set, updates related comments, and removes a corresponding SKIP waiver entry for a multi-GPU MoE test that filtered on CUTLASS and FP8 conditions.

Changes

MoE CUTLASS Skip Logic and Waiver Update

Layer / File(s) Summary
TP alignment skip condition and waiver removal
tests/unittest/_torch/modules/moe/moe_test_utils.py, tests/integration/test_lists/waives.txt
QuantAlgo.MXFP8 added to tp_alignment_quants in should_skip_cutlass with revised comments documenting the 128-aligned per-shard requirement and MXFP4 auto-padding for W4A8_MXFP4_MXFP8; corresponding SKIP waiver entry for test_configurable_moe_multi_gpu removed.

Estimated code review effort: 2 (Simple) | ~10 minutes

Possibly related PRs

Suggested reviewers: taylor-yb-lee, nvchenghaoz

🚥 Pre-merge checks | ✅ 5
✅ Passed checks (5 passed)
Check name Status Explanation
Title check ✅ Passed The title is concise and accurately describes the main change to MXFP8 CUTLASS MoE test skipping.
Docstring Coverage ✅ Passed No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
Description check ✅ Passed The PR description clearly explains the issue, fix, scope, and test coverage, and matches the required template well.
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@xxi-nv
xxi-nv force-pushed the user/xxi/waive-mxfp8-cutlass-tp-align-6402048 branch from 6e37752 to f55a13e Compare July 2, 2026 03:22
@xxi-nv
xxi-nv requested a review from leslie-fang25 July 2, 2026 03:28
…per-shard failure

MXFP8CutlassFusedMoEMethod.create_weights hard-asserts
intermediate_size_per_partition % 128 == 0 for its int32 UE8M0 SF
packing. When moe_tp_size > 1 shards a non-128-aligned intermediate
axis (e.g. Qwen1.5-MoE-A2.7B intermediate_size=1408 with TTP/DTP
moe_tp_size=4 gives per-shard 352), the assertion raises and
test_configurable_moe_multi_gpu fails.

Changes:
- should_skip_cutlass: add QuantAlgo.MXFP8 to tp_alignment_quants so
  non-128-aligned per-shard MXFP8 configs are skipped at param-gen time,
  matching W8A16 / NVFP4 / W4A8_AWQ. Non-sharded non-aligned sizes (e.g.
  GPT-OSS 2880) are already covered by get_quick_skip_reason; plain FP8
  (no alignment assertion) is unaffected.
- waives.txt: remove the now-redundant SKIP entry for this test.
- l0_dgx_b200.yml post-merge: add 'and not MXFP8' so that selector stays
  on plain FP8 QDQ as its comment intends.
- l0_dgx_b200.yml pre-merge: add an explicit 'CUTLASS and MXFP8 and not
  W4A8' entry so aligned MXFP8 configs (DeepSeek-V4/boundary all modes,
  Qwen1.5 EP modes) get real coverage while non-aligned ones auto-skip.

Signed-off-by: xxi <xxi@nvidia.com>
@xxi-nv
xxi-nv force-pushed the user/xxi/waive-mxfp8-cutlass-tp-align-6402048 branch from f55a13e to 8f8088e Compare July 2, 2026 03:47
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xxi-nv enabled auto-merge (squash) July 2, 2026 04:59
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xxi-nv commented Jul 2, 2026

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/bot run --disable-fail-fast

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PR_Github #57119 [ run ] triggered by Bot. Commit: 8f8088e Link to invocation

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PR_Github #57119 [ run ] completed with state SUCCESS. Commit: 8f8088e
/LLM/main/L0_MergeRequest_PR pipeline #45906 completed with status: 'FAILURE'

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/bot run --disable-fail-fast

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xxi-nv commented Jul 2, 2026

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/bot run --disable-fail-fast

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xxi-nv commented Jul 2, 2026

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/bot run --disable-fail-fast

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/bot run --disable-fail-fast

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xxi-nv commented Jul 4, 2026

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/bot run --disable-fail-fast

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PR_Github #57548 [ run ] triggered by Bot. Commit: 2171b35 Link to invocation

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PR_Github #57548 [ run ] completed with state SUCCESS. Commit: 2171b35
/LLM/main/L0_MergeRequest_PR pipeline #46277 completed with status: 'SUCCESS'

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xxi-nv merged commit e4aba85 into NVIDIA:main Jul 4, 2026
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BrianLi23 pushed a commit to BrianLi23/TensorRT-LLM that referenced this pull request Jul 9, 2026
…igned per-shard intermediate (NVIDIA#15865)

Signed-off-by: xxi <xxi@nvidia.com>
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