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[TRTLLM-13642][feat] Add perf sanity tests for Llama-3.1-8B and Gemma-3-1B and verify cache transceiver V2 support - #16355

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Shixiaowei02 merged 7 commits into
NVIDIA:mainfrom
moraxu:dev-mguzek-llama-3.1-8b-cache-transceiver-v2
Jul 27, 2026
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[TRTLLM-13642][feat] Add perf sanity tests for Llama-3.1-8B and Gemma-3-1B and verify cache transceiver V2 support#16355
Shixiaowei02 merged 7 commits into
NVIDIA:mainfrom
moraxu:dev-mguzek-llama-3.1-8b-cache-transceiver-v2

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@moraxu moraxu commented Jul 14, 2026 •
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Summary by CodeRabbit

  • New Features
    • Added GB200 multi-node disaggregated performance sanity testing for Gemma 3 1B and Llama 3.1 8B models.
    • Added support for running these benchmarks with PyTorch across 8 GPUs and two nodes.
    • Added model-path support for Gemma 3 1B Instruct.
  • Test Coverage
    • Added end-to-end performance configurations with BF16, streaming, and 1K input/output workloads.

Description

Adds new perf sanity tests for Llama-3.1-8B and Gemma-3-1B that use the new Python KV cache transceiver V2

Test Coverage

Pre-Merge Perf Results - Llama-3.1-8B

  • Python (v2):
Metric	                        Latest Value
Output Token Throughput (tok/s)	20979.79	
Total Token Throughput (tok/s)	41959.58
  • CPP (v1):
Metric	                        Latest Value
Output Token Throughput (tok/s)	21251.76	
Total Token Throughput (tok/s)	42503.53

Python's Output Token Throughput is 2% lower than CPP's.
Python's Total Token Throughput is 2% lower than CPP's.

Pre-Merge Perf Results - Gemma-3-1B

  1. First run:
  • Python (v2):
Metric	                        Latest Value
Output Token Throughput (tok/s)	48445.12	
Total Token Throughput (tok/s)	96890.23
  • CPP (v1):
Metric	                        Latest Value
Output Token Throughput (tok/s)	41990.30	
Total Token Throughput (tok/s)	83980.61

Python's Output Token Throughput is 15% higher than CPP's.
Python's Total Token Throughput is 15% higher than CPP's.

  1. Second run:
  • Python (v2):
Metric	                        Latest Value
Output Token Throughput (tok/s)	39551.51	
Total Token Throughput (tok/s)	79103.01
  • CPP (v1):
Metric	                        Latest Value
Output Token Throughput (tok/s)	41019.11	
Total Token Throughput (tok/s)	82038.22

Python's Output Token Throughput is 4% lower than CPP's.
Python's Total Token Throughput is 4% lower than CPP's.

PR Checklist

Please review the following before submitting your PR:

  • PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.

  • PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.

  • Test cases are provided for new code paths (see test instructions)

  • If PR introduces API changes, an appropriate PR label is added - either api-compatible or api-breaking. For api-breaking, include BREAKING in the PR title.

  • Any new dependencies have been scanned for license and vulnerabilities

  • CODEOWNERS updated if ownership changes

  • Documentation updated as needed

  • Update tava architecture diagram if there is a significant design change in PR.

  • The reviewers assigned automatically/manually are appropriate for the PR.

  • Please check this after reviewing the above items as appropriate for this PR.

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/bot run --stage-list "GB200-8_GPUs-2_Nodes-PyTorch-Disagg-PerfSanity-CTX1-NODE1-GPU1-GEN1-NODE1-GPU1-Post-Merge-2"

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PR_Github #59096 [ run ] triggered by Bot. Commit: 8d55b8e Link to invocation

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PR_Github #59096 [ run ] completed with state SUCCESS. Commit: 8d55b8e
/LLM/main/L0_MergeRequest_PR pipeline #47610 (Partly Tested) completed with status: 'SUCCESS'

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/bot run --stage-list "GB200-8_GPUs-2_Nodes-PyTorch-Disagg-PerfSanity-CTX1-NODE1-GPU1-GEN1-NODE1-GPU1-Post-Merge-2"

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PR_Github #59238 [ run ] triggered by Bot. Commit: ee8bee0 Link to invocation

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PR_Github #59238 [ run ] completed with state FAILURE. Commit: ee8bee0

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/bot run --stage-list "GB200-8_GPUs-2_Nodes-PyTorch-Disagg-PerfSanity-CTX1-NODE1-GPU1-GEN1-NODE1-GPU1-Post-Merge-2"

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PR_Github #59252 [ run ] triggered by Bot. Commit: ee8bee0 Link to invocation

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PR_Github #59252 [ run ] completed with state SUCCESS. Commit: ee8bee0
/LLM/main/L0_MergeRequest_PR pipeline #47740 (Partly Tested) completed with status: 'SUCCESS'

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/bot run --stage-list "GB200-8_GPUs-2_Nodes-PyTorch-Disagg-PerfSanity-CTX1-NODE1-GPU1-GEN1-NODE1-GPU1-Post-Merge-2" --disable-reuse-test

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PR_Github #59260 [ run ] triggered by Bot. Commit: ee8bee0 Link to invocation

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PR_Github #59260 [ run ] completed with state SUCCESS. Commit: ee8bee0
/LLM/main/L0_MergeRequest_PR pipeline #47748 (Partly Tested) completed with status: 'SUCCESS'

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moraxu requested review from chienchunhung and nv-xtf July 14, 2026 20:40
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chienchunhung approved these changes Jul 14, 2026
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Thanks for the PR! Overall LGTM.

Comment thread jenkins/L0_MergeRequest.groovy Outdated
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nv-xtf marked this pull request as ready for review July 15, 2026 01:56
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PR_Github #61197 [ run ] completed with state FAILURE. Commit: 8981e22
/LLM/main/L0_MergeRequest_PR pipeline #49442 (Partly Tested) completed with status: 'FAILURE'

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/bot run --stage-list "GB200-8_GPUs-2_Nodes-PyTorch-Disagg-PerfSanity-CTX1-NODE1-GPU1-GEN1-NODE1-GPU1-Post-Merge-1,GB200-8_GPUs-2_Nodes-PyTorch-Disagg-PerfSanity-CTX1-NODE1-GPU1-GEN1-NODE1-GPU1-Post-Merge-2"

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PR_Github #61245 [ run ] triggered by Bot. Commit: 8981e22 Link to invocation

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PR_Github #61245 [ run ] completed with state FAILURE. Commit: 8981e22
/LLM/main/L0_MergeRequest_PR pipeline #49481 (Partly Tested) completed with status: 'FAILURE'

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Shixiaowei02 force-pushed the dev-mguzek-llama-3.1-8b-cache-transceiver-v2 branch from 8981e22 to a4cf0df Compare July 23, 2026 08:49
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/bot run --stage-list "GB200-8_GPUs-2_Nodes-PyTorch-Disagg-PerfSanity-CTX1-NODE1-GPU1-GEN1-NODE1-GPU1-Post-Merge-1,GB200-8_GPUs-2_Nodes-PyTorch-Disagg-PerfSanity-CTX1-NODE1-GPU1-GEN1-NODE1-GPU1-Post-Merge-2"

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PR_Github #61348 [ run ] triggered by Bot. Commit: a4cf0df Link to invocation

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PR_Github #61348 [ run ] completed with state FAILURE. Commit: a4cf0df
/LLM/main/L0_MergeRequest_PR pipeline #49576 (Partly Tested) completed with status: 'FAILURE'

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⚠️ Action Required:

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/bot run --stage-list "GB200-8_GPUs-2_Nodes-PyTorch-Disagg-PerfSanity-CTX1-NODE1-GPU1-GEN1-NODE1-GPU1-Post-Merge-1,GB200-8_GPUs-2_Nodes-PyTorch-Disagg-PerfSanity-CTX1-NODE1-GPU1-GEN1-NODE1-GPU1-Post-Merge-2"

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PR_Github #61353 [ run ] triggered by Bot. Commit: a4cf0df Link to invocation

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PR_Github #61353 [ run ] completed with state FAILURE. Commit: a4cf0df
/LLM/main/L0_MergeRequest_PR pipeline #49581 (Partly Tested) completed with status: 'FAILURE'

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⚠️ Action Required:

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moraxu added 7 commits July 26, 2026 22:16
@moraxu
First draft
8eb788e 
Signed-off-by: Michal Guzek <mguzek@nvidia.com>
@moraxu
Switch to v2
49bdbc1 
Signed-off-by: Michal Guzek <mguzek@nvidia.com>
@moraxu
Revert back to CPP
b96ef16 
Signed-off-by: Michal Guzek <mguzek@nvidia.com>
@moraxu
Final version
7baf244 
Signed-off-by: Michal Guzek <mguzek@nvidia.com>
@moraxu
First draft - CPP backend
e1b0328 
Signed-off-by: Michal Guzek <mguzek@nvidia.com>
@moraxu
Update runtime
958027f 
Signed-off-by: Michal Guzek <mguzek@nvidia.com>
@moraxu
Remove tests from L0
12b94d3 
Signed-off-by: Michal Guzek <mguzek@nvidia.com>
@moraxu
moraxu force-pushed the dev-mguzek-llama-3.1-8b-cache-transceiver-v2 branch from a4cf0df to 12b94d3 Compare July 27, 2026 05:17
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/bot help

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/bot skip

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Launch build/test pipelines. All previously running jobs will be killed.

--reuse-test (optional)pipeline-id (OPTIONAL) : Allow the new pipeline to reuse build artifacts and skip successful test stages from a specified pipeline or the last pipeline if no pipeline-id is indicated. If the Git commit ID has changed, this option will be always ignored. The DEFAULT behavior of the bot is to reuse build artifacts and successful test results from the last pipeline.

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--gpu-type "A30, H100_PCIe" (OPTIONAL) : Only run the test stages on the specified GPU types. Examples: "A30, H100_PCIe". Note: Does NOT update GitHub check status.

--test-backend "pytorch, cpp" (OPTIONAL) : Skip test stages which don't match the specified backends. Only support [pytorch, cpp, tensorrt, triton]. Examples: "pytorch, cpp" (does not run test stages with tensorrt or triton backend). Note: Does NOT update GitHub pipeline status.

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/bot skip --comment "Only YAML files were modified"

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PR_Github #61812 [ skip ] triggered by Bot. Commit: 12b94d3 Link to invocation

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PR_Github #61812 [ skip ] completed with state SUCCESS. Commit: 12b94d3
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Shixiaowei02 merged commit b91ffda into NVIDIA:main Jul 27, 2026
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hhzhang16 added a commit to hhzhang16/TensorRT-LLM that referenced this pull request Jul 27, 2026
@hhzhang16
Merge branch 'main' of https://github.com/NVIDIA/TensorRT-LLM into ha…
3340b41 
…nnahz/dep-1083-port-flashinfer-stable-va-lifecycle-for-native-all-reduce

* 'main' of https://github.com/NVIDIA/TensorRT-LLM: (54 commits)
  [NVIDIA#15673][fix] Enable CUDA core fast path for SM89/SM120/SM121 (NVIDIA#12705)
  [None][test] Adjust timeout cases in QA perf test (NVIDIA#16894)
  [https://nvbugs/6157892][fix] Mistral format refactor (NVIDIA#15123)
  [None][feat] Add kimi_k2/glm_5 grouped routing and fused router to bench_moe (NVIDIA#16830)
  [https://nvbugs/6501376][fix] Test-only fix — drop the `if hidden_size % 2 != 0: with pytest.raises(...)`… (NVIDIA#16844)
  [TRTLLM-13642][feat] Add perf sanity tests for Llama-3.1-8B and Gemma-3-1B and verify cache transceiver V2 support (NVIDIA#16355)
  [https://nvbugs/6433376][fix] Update the Dense test to mirror the MoE sibling — assert `bfloat16` under… (NVIDIA#16203)
  [None][fix] Resolve NVFP4 mixed-precision base layers for the DSpark draft (NVIDIA#16831)
  [https://nvbugs/6479324][test] Remove waiver for fixed qwen3_5_4b_fp8_stress disaggregated stress test (NVIDIA#16878)
  [https://nvbugs/6507109][infra] Split slow DGX B300 attention unit tests (NVIDIA#16838)
  [None][infra] Waive 21 failed cases for main in post-merge 2862 (NVIDIA#16882)
  [None][perf] prepare_inputs: avoid O(seq_len) get_tokens(0) marshalling on the host (NVIDIA#16791)
  [None][perf] Optimize Blackwell fused MHC half-MMA kernel (NVIDIA#16799)
  [None][infra] Auto-update test durations from OpenSearch (last 7 days)
  [None][perf] Skip DeepGEMM clean_logits in DSA indexer prefill on custom top-k path (NVIDIA#16789)
  [None][feat] Support DeepSeek-V4 in layer_wise_benchmarks (NVIDIA#16774)
  [https://nvbugs/6465993][fix] use attention cache dtype for disaggregated transfer (NVIDIA#16505)
  [https://nvbugs/6463822][fix] Fix LTX2 CUDA graph test leak issue (NVIDIA#16775)
  [https://nvbugs/5948435][chore] Unwaive DeepSeekV3Lite test_nvfp4_4gpus CUTLASS ep4 fp8kv on RTXPro6000D (NVIDIA#16621)
  [TRTLLM-14417][fix] Exclude ADP/cuda-graph dummy requests from speculative-decode acceptance stats (NVIDIA#16571)
  ...

Signed-off-by: Hannah Zhang <hannahz@nvidia.com>
hhzhang16 added a commit to hhzhang16/TensorRT-LLM that referenced this pull request Jul 27, 2026
@hhzhang16
Merge branch 'main' of https://github.com/NVIDIA/TensorRT-LLM into ha…
e064a65 
…nnahz/dep-1082-shared-mnnvl-moe-lifecycle

* 'main' of https://github.com/NVIDIA/TensorRT-LLM: (142 commits)
  [NVIDIA#15673][fix] Enable CUDA core fast path for SM89/SM120/SM121 (NVIDIA#12705)
  [None][test] Adjust timeout cases in QA perf test (NVIDIA#16894)
  [https://nvbugs/6157892][fix] Mistral format refactor (NVIDIA#15123)
  [None][feat] Add kimi_k2/glm_5 grouped routing and fused router to bench_moe (NVIDIA#16830)
  [https://nvbugs/6501376][fix] Test-only fix — drop the `if hidden_size % 2 != 0: with pytest.raises(...)`… (NVIDIA#16844)
  [TRTLLM-13642][feat] Add perf sanity tests for Llama-3.1-8B and Gemma-3-1B and verify cache transceiver V2 support (NVIDIA#16355)
  [https://nvbugs/6433376][fix] Update the Dense test to mirror the MoE sibling — assert `bfloat16` under… (NVIDIA#16203)
  [None][fix] Resolve NVFP4 mixed-precision base layers for the DSpark draft (NVIDIA#16831)
  [https://nvbugs/6479324][test] Remove waiver for fixed qwen3_5_4b_fp8_stress disaggregated stress test (NVIDIA#16878)
  [https://nvbugs/6507109][infra] Split slow DGX B300 attention unit tests (NVIDIA#16838)
  [None][infra] Waive 21 failed cases for main in post-merge 2862 (NVIDIA#16882)
  [None][perf] prepare_inputs: avoid O(seq_len) get_tokens(0) marshalling on the host (NVIDIA#16791)
  [None][perf] Optimize Blackwell fused MHC half-MMA kernel (NVIDIA#16799)
  [None][infra] Auto-update test durations from OpenSearch (last 7 days)
  [None][perf] Skip DeepGEMM clean_logits in DSA indexer prefill on custom top-k path (NVIDIA#16789)
  [None][feat] Support DeepSeek-V4 in layer_wise_benchmarks (NVIDIA#16774)
  [https://nvbugs/6465993][fix] use attention cache dtype for disaggregated transfer (NVIDIA#16505)
  [https://nvbugs/6463822][fix] Fix LTX2 CUDA graph test leak issue (NVIDIA#16775)
  [https://nvbugs/5948435][chore] Unwaive DeepSeekV3Lite test_nvfp4_4gpus CUTLASS ep4 fp8kv on RTXPro6000D (NVIDIA#16621)
  [TRTLLM-14417][fix] Exclude ADP/cuda-graph dummy requests from speculative-decode acceptance stats (NVIDIA#16571)
  ...

Signed-off-by: Hannah Zhang <hannahz@nvidia.com>
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@chienchunhung chienchunhung chienchunhung approved these changes
@Shixiaowei02 Shixiaowei02 Shixiaowei02 approved these changes
@BowenFu BowenFu BowenFu approved these changes
@dhansen-nvidia dhansen-nvidia dhansen-nvidia approved these changes
@fredricz-20070104 fredricz-20070104 fredricz-20070104 approved these changes
@dpitman-nvda dpitman-nvda dpitman-nvda approved these changes
@nv-xtf nv-xtf nv-xtf approved these changes
@nv-ananjappa nv-ananjappa Awaiting requested review from nv-ananjappa nv-ananjappa is a code owner automatically assigned from NVIDIA/trt-llm-perf-devs
@brnguyen2 brnguyen2 Awaiting requested review from brnguyen2 brnguyen2 is a code owner automatically assigned from NVIDIA/trt-llm-devs
@yiqingy0 yiqingy0 Awaiting requested review from yiqingy0 yiqingy0 is a code owner automatically assigned from NVIDIA/trt-llm-infra-devs
@chenfeiz0326 chenfeiz0326 Awaiting requested review from chenfeiz0326
@reasonsolo reasonsolo Awaiting requested review from reasonsolo reasonsolo is a code owner automatically assigned from NVIDIA/trt-llm-disagg-devs
@bo-nv bo-nv Awaiting requested review from bo-nv bo-nv is a code owner automatically assigned from NVIDIA/trt-llm-disagg-devs

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@moraxu @tensorrt-cicd @Shixiaowei02 @chienchunhung @BowenFu @dhansen-nvidia @fredricz-20070104 @dpitman-nvda @nv-xtf