[None][feat] Support DeepSeek-V4 in layer_wise_benchmarks - #16774
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DeepSeek-V4's multi-head hyper-connection (mHC) decoder layers do not fit the generic single-layer harness in tools/layer_wise_benchmarks/runner.py: - create_kv_cache_manager: the is_mla branch omitted vocab_size, which DeepseekV4CacheManager.__init__ requires (keyword-only, no default). - create_run_pack: V4 layers take the initial residual as hc_state shaped [num_tokens, hc_mult, hidden_size] and their MoE routing needs input_ids; both are now synthesized when the config exposes hc_mult. - run_pack(check=True): guarded the NaN/Inf/zero check with isinstance since mHC layers return an HCState, not a Tensor. Non-V4 models are unaffected (all V4 paths gate on hc_mult / MLA class). Usage for V4: --moe-backend DEEPGEMM and a --layer-indices slice that starts at layer 0 and covers both compress ratios (e.g. 0,1,2,3). Signed-off-by: Ruodi Lu <ruodil@users.noreply.github.com>
WalkthroughThe layer-wise benchmark runner now prepares DeepSeek-V4 hyper-connection inputs, conditionally validates tensor outputs, and passes vocabulary size when constructing MLA KV-cache managers. ChangesBenchmark runner behavior
Estimated code review effort: 2 (Simple) | ~10 minutes Suggested reviewers: 🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches🧪 Generate unit tests (beta)
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tensorrt_llm/tools/layer_wise_benchmarks/runner.py (1)
664-678: 📐 Maintainability & Code Quality | 🔵 Trivial | ⚡ Quick winAdd a regression test for the V4 input contract.
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hc_mult=4and a non-V4 configuration, asserting the expanded hidden-state shape and generatedinput_idsdtype/range. DeepSeek-V4 relies on expanded mHC residual streams and token-ID-based hash routing. (nvidia.github.io)🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@tensorrt_llm/tools/layer_wise_benchmarks/runner.py` around lines 664 - 678, Add a regression test covering the input-preparation logic around the hc_mult handling, using hc_mult=4 and a non-V4 configuration. Assert that V4 hidden states expand to [num_tokens, 4, hidden_size], generated input_ids use torch.int32 and remain within [0, vocab_size), while the non-V4 path preserves the original hidden-state shape and does not add input_ids.
🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
Nitpick comments:
In `@tensorrt_llm/tools/layer_wise_benchmarks/runner.py`:
- Around line 664-678: Add a regression test covering the input-preparation
logic around the hc_mult handling, using hc_mult=4 and a non-V4 configuration.
Assert that V4 hidden states expand to [num_tokens, 4, hidden_size], generated
input_ids use torch.int32 and remain within [0, vocab_size), while the non-V4
path preserves the original hidden-state shape and does not add input_ids.
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tensorrt_llm/tools/layer_wise_benchmarks/runner.py
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…nnahz/dep-1083-port-flashinfer-stable-va-lifecycle-for-native-all-reduce * 'main' of https://github.com/NVIDIA/TensorRT-LLM: (54 commits) [NVIDIA#15673][fix] Enable CUDA core fast path for SM89/SM120/SM121 (NVIDIA#12705) [None][test] Adjust timeout cases in QA perf test (NVIDIA#16894) [https://nvbugs/6157892][fix] Mistral format refactor (NVIDIA#15123) [None][feat] Add kimi_k2/glm_5 grouped routing and fused router to bench_moe (NVIDIA#16830) [https://nvbugs/6501376][fix] Test-only fix — drop the `if hidden_size % 2 != 0: with pytest.raises(...)`… (NVIDIA#16844) [TRTLLM-13642][feat] Add perf sanity tests for Llama-3.1-8B and Gemma-3-1B and verify cache transceiver V2 support (NVIDIA#16355) [https://nvbugs/6433376][fix] Update the Dense test to mirror the MoE sibling — assert `bfloat16` under… (NVIDIA#16203) [None][fix] Resolve NVFP4 mixed-precision base layers for the DSpark draft (NVIDIA#16831) [https://nvbugs/6479324][test] Remove waiver for fixed qwen3_5_4b_fp8_stress disaggregated stress test (NVIDIA#16878) [https://nvbugs/6507109][infra] Split slow DGX B300 attention unit tests (NVIDIA#16838) [None][infra] Waive 21 failed cases for main in post-merge 2862 (NVIDIA#16882) [None][perf] prepare_inputs: avoid O(seq_len) get_tokens(0) marshalling on the host (NVIDIA#16791) [None][perf] Optimize Blackwell fused MHC half-MMA kernel (NVIDIA#16799) [None][infra] Auto-update test durations from OpenSearch (last 7 days) [None][perf] Skip DeepGEMM clean_logits in DSA indexer prefill on custom top-k path (NVIDIA#16789) [None][feat] Support DeepSeek-V4 in layer_wise_benchmarks (NVIDIA#16774) [https://nvbugs/6465993][fix] use attention cache dtype for disaggregated transfer (NVIDIA#16505) [https://nvbugs/6463822][fix] Fix LTX2 CUDA graph test leak issue (NVIDIA#16775) [https://nvbugs/5948435][chore] Unwaive DeepSeekV3Lite test_nvfp4_4gpus CUTLASS ep4 fp8kv on RTXPro6000D (NVIDIA#16621) [TRTLLM-14417][fix] Exclude ADP/cuda-graph dummy requests from speculative-decode acceptance stats (NVIDIA#16571) ... Signed-off-by: Hannah Zhang <hannahz@nvidia.com>
…nnahz/dep-1082-shared-mnnvl-moe-lifecycle * 'main' of https://github.com/NVIDIA/TensorRT-LLM: (142 commits) [NVIDIA#15673][fix] Enable CUDA core fast path for SM89/SM120/SM121 (NVIDIA#12705) [None][test] Adjust timeout cases in QA perf test (NVIDIA#16894) [https://nvbugs/6157892][fix] Mistral format refactor (NVIDIA#15123) [None][feat] Add kimi_k2/glm_5 grouped routing and fused router to bench_moe (NVIDIA#16830) [https://nvbugs/6501376][fix] Test-only fix — drop the `if hidden_size % 2 != 0: with pytest.raises(...)`… (NVIDIA#16844) [TRTLLM-13642][feat] Add perf sanity tests for Llama-3.1-8B and Gemma-3-1B and verify cache transceiver V2 support (NVIDIA#16355) [https://nvbugs/6433376][fix] Update the Dense test to mirror the MoE sibling — assert `bfloat16` under… (NVIDIA#16203) [None][fix] Resolve NVFP4 mixed-precision base layers for the DSpark draft (NVIDIA#16831) [https://nvbugs/6479324][test] Remove waiver for fixed qwen3_5_4b_fp8_stress disaggregated stress test (NVIDIA#16878) [https://nvbugs/6507109][infra] Split slow DGX B300 attention unit tests (NVIDIA#16838) [None][infra] Waive 21 failed cases for main in post-merge 2862 (NVIDIA#16882) [None][perf] prepare_inputs: avoid O(seq_len) get_tokens(0) marshalling on the host (NVIDIA#16791) [None][perf] Optimize Blackwell fused MHC half-MMA kernel (NVIDIA#16799) [None][infra] Auto-update test durations from OpenSearch (last 7 days) [None][perf] Skip DeepGEMM clean_logits in DSA indexer prefill on custom top-k path (NVIDIA#16789) [None][feat] Support DeepSeek-V4 in layer_wise_benchmarks (NVIDIA#16774) [https://nvbugs/6465993][fix] use attention cache dtype for disaggregated transfer (NVIDIA#16505) [https://nvbugs/6463822][fix] Fix LTX2 CUDA graph test leak issue (NVIDIA#16775) [https://nvbugs/5948435][chore] Unwaive DeepSeekV3Lite test_nvfp4_4gpus CUTLASS ep4 fp8kv on RTXPro6000D (NVIDIA#16621) [TRTLLM-14417][fix] Exclude ADP/cuda-graph dummy requests from speculative-decode acceptance stats (NVIDIA#16571) ... Signed-off-by: Hannah Zhang <hannahz@nvidia.com>
DeepSeek-V4's multi-head hyper-connection (mHC) decoder layers do not fit the generic single-layer harness in tools/layer_wise_benchmarks/runner.py:
Non-V4 models are unaffected (all V4 paths gate on hc_mult / MLA class).
Usage for V4: --moe-backend DEEPGEMM and a --layer-indices slice that starts at layer 0 and covers both compress ratios (e.g. 0,1,2,3).
Dev Engineer Review
runner.pyby:vocab_sizeto the MLA KV-cache manager.hc_stateandinput_idsfor mHC layers.--moe-backend DEEPGEMMand layer indices beginning at 0 and covering both compression ratios, e.g.0,1,2,3.QA Engineer Review
No test changes.
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