[https://nvbugs/6501376][fix] Test-only fix — drop the `if hidden_size % 2 != 0: with pytest.raises(...)`… by trtllm-agent · Pull Request #16844 · NVIDIA/TensorRT-LLM

trtllm-agent · 2026-07-24T16:59:01Z

Summary

Root cause: Stale pytest.raises(AssertionError) on the odd-hidden_size branch expected a divisibility assert that PR [TRTLLM-13117][feat] Implement Uneven TP Linear for VisualGen models #14875's _auto_tp_sharding no longer fires for VANILLA row/column Linear.
Fix: Test-only fix — drop the if hidden_size % 2 != 0: with pytest.raises(...) branch in both test_row_linear and test_column_linear; unconditionally for r in results: assert r is True.
Automated fix generated by repair-bot

Test plan

Verify fix on the same GPU type as the original failure
Check for regressions in related tests

Links

Bug: https://nvbugs/6501376

Dev Engineer Review

Updated tensorrt_llm/_torch/modules/linear.py to correctly handle gather_output=True for VANILLA TensorParallelMode.COLUMN when _auto_tp_sharding produces uneven per-rank shard widths:
- Added _tp_sharding_is_auto tracking to distinguish whether tp_sharding came from _auto_tp_sharding vs override_tp_sharding.
- Extended gather_output_sizes (default None) to store per-rank allgather sizes when uneven widths are detected.
- Updated _auto_tp_sharding(..., rank=...) to accept an optional rank argument so shard boundaries can be queried for other ranks.
- In forward for COLUMN + gather_output=True, passed sizes=self.gather_output_sizes into the COLUMN allgather to avoid relying on shape inference.
- Added validation rejecting incompatible combinations of gather_output with override_tp_sharding (via a ValueError), aligning with the referenced bug about this unsupported mode combination.
Updated tests/unittest/_torch/multi_gpu/test_linear.py:
- Removed conditional pytest.raises(AssertionError) expectations for “unbalanced/odd” hidden_size in both test_column_linear and test_row_linear.
- Tests now always iterate through results and assert each rank returns True, reflecting the post-[TRTLLM-13117][feat] Implement Uneven TP Linear for VisualGen models #14875 behavior where _auto_tp_sharding no longer triggers that assertion for odd hidden sizes.

QA Engineer Review

Modified test code (tests/unittest/_torch/multi_gpu/test_linear.py):
- Modified: test_column_linear (removed conditional failure expectation; now asserts True for all ranks)
- Modified: test_row_linear (removed conditional failure expectation; now asserts True for all ranks)
Modified test-list file (tests/integration/test_lists/waives.txt):
- Removed SKIP entries:
  - unittest/_torch/multi_gpu/test_linear.py::test_column_linear[2-unbalanced]
  - unittest/_torch/multi_gpu/test_linear.py::test_row_linear[2-unbalanced]
Verdict: needs follow-up (CI was mentioned as triggered/aborted/killed, but no CBTS coverage data or test failure details were provided in the context).

…mn linear PR NVIDIA#14875 added VANILLA-mode uneven-TP support in tensorrt_llm/_torch/modules/linear.py via _auto_tp_sharding, so test_row_linear[2-unbalanced] (hidden=15) and test_column_linear [2-unbalanced] (hidden=127) no longer hit the divisibility assert. The pre-existing tests still expected an AssertionError on the odd branch, producing "Failed: DID NOT RAISE" in pre-merge CI. Unconditionally assert all ranks return True. Signed-off-by: handongl <handongl@nvidia.com>

coderabbitai · 2026-07-24T17:02:11Z

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📒 Files selected for processing (1)

tensorrt_llm/_torch/modules/linear.py

🚧 Files skipped from review as they are similar to previous changes (1)

tensorrt_llm/_torch/modules/linear.py

Walkthrough

Linear now computes per-rank sizes for uneven column-parallel outputs and supplies them to allgather. Multi-GPU column and row linear tests no longer expect failures for odd hidden sizes, and related skip waivers are removed.

Changes

Uneven linear sharding

Layer / File(s)	Summary
Compute and apply uneven gather sizes `tensorrt_llm/_torch/modules/linear.py`	`Linear` tracks auto-generated sharding, derives per-rank output widths, validates unsupported overrides, and passes sizes to column allgather.
Enable unbalanced linear tests `tests/unittest/_torch/multi_gpu/test_linear.py`, `tests/integration/test_lists/waives.txt`	Column and row tests now require successful results for odd hidden sizes, and their skip waivers are removed.

Estimated code review effort: 2 (Simple) | ~10 minutes

Sequence Diagram(s)

sequenceDiagram
  participant LinearInit
  participant AutoTPSharding
  participant LinearForward
  participant Allgather
  LinearInit->>AutoTPSharding: Query per-rank shard widths
  AutoTPSharding-->>LinearInit: Return shard boundaries
  LinearForward->>Allgather: Pass gather_output_sizes
  Allgather-->>LinearForward: Gather uneven column outputs

Possibly related PRs

NVIDIA/TensorRT-LLM#14875: Addresses related uneven tensor-parallel sharding behavior in Linear and unbalanced linear tests.
NVIDIA/TensorRT-LLM#16840: Updates the same multi-GPU linear tests and related waiver entries.
NVIDIA/TensorRT-LLM#16870: Also changes column-linear handling for uneven gather_output sharding.

Suggested labels: VisualGen

Suggested reviewers: qijune, xinhe-nv, brnguyen2, bowenfu, jieli-matrix

🚥 Pre-merge checks | ✅ 3 | ❌ 2

❌ Failed checks (2 warnings)

Check name	Status	Explanation	Resolution
Description check	⚠️ Warning	The description covers the fix and test plan, but it omits the required Description, Test Coverage, and PR Checklist sections from the template.	Add the missing template sections: Description, Test Coverage, and PR Checklist, and fill them out with a brief issue/solution summary and validation details.
Docstring Coverage	⚠️ Warning	Docstring coverage is 50.00% which is insufficient. The required threshold is 80.00%.	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (3 passed)

Check name	Status	Explanation
Title check	✅ Passed	The title is clearly related to the change and identifies the bug fix, though it is longer and less concise than ideal.
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
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Signed-off-by: junq <22017000+QiJune@users.noreply.github.com>

QiJune · 2026-07-25T12:47:41Z

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StanleySun639

Should we close #16840? That looks like an incomplete fix.

lori-ren · 2026-07-27T03:09:26Z

Should we close #16840? That looks like an incomplete fix.

I plan to close it after this one is merged

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…nnahz/dep-1083-port-flashinfer-stable-va-lifecycle-for-native-all-reduce * 'main' of https://github.com/NVIDIA/TensorRT-LLM: (54 commits) [NVIDIA#15673][fix] Enable CUDA core fast path for SM89/SM120/SM121 (NVIDIA#12705) [None][test] Adjust timeout cases in QA perf test (NVIDIA#16894) [https://nvbugs/6157892][fix] Mistral format refactor (NVIDIA#15123) [None][feat] Add kimi_k2/glm_5 grouped routing and fused router to bench_moe (NVIDIA#16830) [https://nvbugs/6501376][fix] Test-only fix — drop the `if hidden_size % 2 != 0: with pytest.raises(...)`… (NVIDIA#16844) [TRTLLM-13642][feat] Add perf sanity tests for Llama-3.1-8B and Gemma-3-1B and verify cache transceiver V2 support (NVIDIA#16355) [https://nvbugs/6433376][fix] Update the Dense test to mirror the MoE sibling — assert `bfloat16` under… (NVIDIA#16203) [None][fix] Resolve NVFP4 mixed-precision base layers for the DSpark draft (NVIDIA#16831) [https://nvbugs/6479324][test] Remove waiver for fixed qwen3_5_4b_fp8_stress disaggregated stress test (NVIDIA#16878) [https://nvbugs/6507109][infra] Split slow DGX B300 attention unit tests (NVIDIA#16838) [None][infra] Waive 21 failed cases for main in post-merge 2862 (NVIDIA#16882) [None][perf] prepare_inputs: avoid O(seq_len) get_tokens(0) marshalling on the host (NVIDIA#16791) [None][perf] Optimize Blackwell fused MHC half-MMA kernel (NVIDIA#16799) [None][infra] Auto-update test durations from OpenSearch (last 7 days) [None][perf] Skip DeepGEMM clean_logits in DSA indexer prefill on custom top-k path (NVIDIA#16789) [None][feat] Support DeepSeek-V4 in layer_wise_benchmarks (NVIDIA#16774) [https://nvbugs/6465993][fix] use attention cache dtype for disaggregated transfer (NVIDIA#16505) [https://nvbugs/6463822][fix] Fix LTX2 CUDA graph test leak issue (NVIDIA#16775) [https://nvbugs/5948435][chore] Unwaive DeepSeekV3Lite test_nvfp4_4gpus CUTLASS ep4 fp8kv on RTXPro6000D (NVIDIA#16621) [TRTLLM-14417][fix] Exclude ADP/cuda-graph dummy requests from speculative-decode acceptance stats (NVIDIA#16571) ... Signed-off-by: Hannah Zhang <hannahz@nvidia.com>

…nnahz/dep-1082-shared-mnnvl-moe-lifecycle * 'main' of https://github.com/NVIDIA/TensorRT-LLM: (142 commits) [NVIDIA#15673][fix] Enable CUDA core fast path for SM89/SM120/SM121 (NVIDIA#12705) [None][test] Adjust timeout cases in QA perf test (NVIDIA#16894) [https://nvbugs/6157892][fix] Mistral format refactor (NVIDIA#15123) [None][feat] Add kimi_k2/glm_5 grouped routing and fused router to bench_moe (NVIDIA#16830) [https://nvbugs/6501376][fix] Test-only fix — drop the `if hidden_size % 2 != 0: with pytest.raises(...)`… (NVIDIA#16844) [TRTLLM-13642][feat] Add perf sanity tests for Llama-3.1-8B and Gemma-3-1B and verify cache transceiver V2 support (NVIDIA#16355) [https://nvbugs/6433376][fix] Update the Dense test to mirror the MoE sibling — assert `bfloat16` under… (NVIDIA#16203) [None][fix] Resolve NVFP4 mixed-precision base layers for the DSpark draft (NVIDIA#16831) [https://nvbugs/6479324][test] Remove waiver for fixed qwen3_5_4b_fp8_stress disaggregated stress test (NVIDIA#16878) [https://nvbugs/6507109][infra] Split slow DGX B300 attention unit tests (NVIDIA#16838) [None][infra] Waive 21 failed cases for main in post-merge 2862 (NVIDIA#16882) [None][perf] prepare_inputs: avoid O(seq_len) get_tokens(0) marshalling on the host (NVIDIA#16791) [None][perf] Optimize Blackwell fused MHC half-MMA kernel (NVIDIA#16799) [None][infra] Auto-update test durations from OpenSearch (last 7 days) [None][perf] Skip DeepGEMM clean_logits in DSA indexer prefill on custom top-k path (NVIDIA#16789) [None][feat] Support DeepSeek-V4 in layer_wise_benchmarks (NVIDIA#16774) [https://nvbugs/6465993][fix] use attention cache dtype for disaggregated transfer (NVIDIA#16505) [https://nvbugs/6463822][fix] Fix LTX2 CUDA graph test leak issue (NVIDIA#16775) [https://nvbugs/5948435][chore] Unwaive DeepSeekV3Lite test_nvfp4_4gpus CUTLASS ep4 fp8kv on RTXPro6000D (NVIDIA#16621) [TRTLLM-14417][fix] Exclude ADP/cuda-graph dummy requests from speculative-decode acceptance stats (NVIDIA#16571) ... Signed-off-by: Hannah Zhang <hannahz@nvidia.com>

trtllm-agent requested a review from a team as a code owner July 24, 2026 16:59

trtllm-agent requested review from YihuiLu512 and lori-ren July 24, 2026 16:59

github-actions Bot assigned trtllm-agent Jul 24, 2026

[nvbugs/6501376][fix] Remove uneven linear test waivers

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QiJune requested review from a team as code owners July 25, 2026 12:35

QiJune requested review from BowenFu, EmmaQiaoCh, QiJune, StanleySun639, jieli-matrix and tburt-nv July 25, 2026 12:35

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QiJune enabled auto-merge (squash) July 25, 2026 12:48

[nvbugs/6501376][fix] Pass per-rank sizes to uneven-TP column linear …

3c09b66

…allgather Signed-off-by: Lori Ren <lorir@nvidia.com>

jieli-matrix removed their request for review July 27, 2026 02:08

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QiJune merged commit 7982aa9 into NVIDIA:main Jul 27, 2026
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lori-ren mentioned this pull request Jul 27, 2026

[https://nvbugs/6501394][fix] Amend the attempt 0 commit to also delete the single waives.txt line… #16840

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JunyiXu-nv mentioned this pull request Jul 30, 2026

[TRTLLM-13409][fix] hard-kill all ranks when one rank's executor loop crashes #16592

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