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[TRTLLM-14540][perf] Skip fp32 state round-trip in FlashInfer GDN pre…#16703

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nv-guomingz:user/guomingz/remove_prefill_cast
Jul 23, 2026
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[TRTLLM-14540][perf] Skip fp32 state round-trip in FlashInfer GDN pre…#16703
nv-guomingz merged 1 commit into
NVIDIA:mainfrom
nv-guomingz:user/guomingz/remove_prefill_cast

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@nv-guomingz nv-guomingz commented Jul 22, 2026

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…fill on SM100/SM103

FlashInfer's SM100/SM103 GDN prefill kernel carries the recurrent state in fp32 in TMEM regardless of the initial/output-state I/O dtype, so the adapter no longer needs to up-cast the gathered state to fp32 and down-cast the final state back. Keep the state in its native pool dtype (bf16/fp16) across the FlashInfer boundary there, halving the state bytes moved by the gather/scatter and dropping the fp32 scratch buffer. SM90/SM120, whose kernels still require fp32 state, are unchanged; the recurrent accumulation stays in fp32, so the result is numerically identical.

image

Dev Engineer Review

  • Updated FlashInfer GDN prefill state handling for SM100/SM103 to retain bf16/fp16 state dtype, reducing gather/scatter memory traffic and eliminating unnecessary fp32 scratch storage.
  • Preserved fp32 state handling for SM90/SM120 and fp32 recurrent accumulation.
  • Added an optional out_dtype parameter to gather_cast_vk_to_fp32_vk, maintaining fp32 as the default for API compatibility.
  • Documentation and state packing behavior were clarified. No configuration or test-list changes were identified.

QA Engineer Review

No test changes.

Description

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Please review the following before submitting your PR:

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@nv-guomingz
nv-guomingz requested a review from a team as a code owner July 22, 2026 02:54
…fill on SM100/SM103

FlashInfer's SM100/SM103 GDN prefill kernel carries the recurrent state in
fp32 in TMEM regardless of the initial/output-state I/O dtype, so the adapter
no longer needs to up-cast the gathered state to fp32 and down-cast the final
state back. Keep the state in its native pool dtype (bf16/fp16) across the
FlashInfer boundary there, halving the state bytes moved by the gather/scatter
and dropping the fp32 scratch buffer. SM90/SM120, whose kernels still require
fp32 state, are unchanged; the recurrent accumulation stays in fp32, so the
result is numerically identical.

Signed-off-by: nv-guomingz <137257613+nv-guomingz@users.noreply.github.com>
@nv-guomingz
nv-guomingz force-pushed the user/guomingz/remove_prefill_cast branch from 443b266 to 1a4eef1 Compare July 22, 2026 02:54
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/bot run --diable-fail-fast

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coderabbitai Bot commented Jul 22, 2026

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Review Change Stack

Walkthrough

The FlashInfer chunk wrapper now selects state dtype by GPU architecture, passes it through gathered initial state, and uses it for optional state buffering. The gather helper supports configurable output dtype while defaulting to fp32.

Changes

SSM state dtype handling

Layer / File(s) Summary
Configurable gathered-state output dtype
tensorrt_llm/_torch/modules/fla/fused_state_io.py
gather_cast_vk_to_fp32_vk accepts an optional output dtype and allocates gathered state using it, defaulting to torch.float32.
GPU-specific FlashInfer state policy
tensorrt_llm/_torch/modules/fla/flashinfer_chunk.py
The wrapper selects native state dtypes on SM100/SM103, uses fp32 elsewhere, and applies the selection to initial-state gathering and state-buffer allocation.

Estimated code review effort: 2 (Simple) | ~10 minutes

Suggested reviewers: asfiyab-nvidia

🚥 Pre-merge checks | ✅ 5
✅ Passed checks (5 passed)
Check name Status Explanation
Docstring Coverage ✅ Passed No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
Title check ✅ Passed The title clearly summarizes the FlashInfer GDN fp32 state round-trip optimization and includes the ticket reference.
Description check ✅ Passed The PR description explains the SM100/SM103 change and rationale, and is mostly complete despite the blank Test Coverage section.
✨ Finishing Touches
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/bot run --disable-fail-fast

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/bot run --disable-fail-fast

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PR_Github #60929 [ run ] triggered by Bot. Commit: 1a4eef1 Link to invocation

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PR_Github #60929 [ run ] completed with state FAILURE. Commit: 1a4eef1
/LLM/main/L0_MergeRequest_PR pipeline #49194 completed with status: 'FAILURE'

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/bot run --diable-fail-fast

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PR_Github #60980 Bot args parsing error: usage: /bot [-h]
{run,kill,skip,submit,reviewers,reuse-pipeline,reuse-review} ...
/bot: error: unrecognized arguments: --diable-fail-fast

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/bot run --disable-fail-fast

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PR_Github #60999 [ run ] triggered by Bot. Commit: 1a4eef1 Link to invocation

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PR_Github #60999 [ run ] completed with state SUCCESS. Commit: 1a4eef1
/LLM/main/L0_MergeRequest_PR pipeline #49257 completed with status: 'SUCCESS'

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nv-guomingz merged commit a19410e into NVIDIA:main Jul 23, 2026
19 checks passed
hhzhang16 added a commit to hhzhang16/TensorRT-LLM that referenced this pull request Jul 23, 2026
…nnahz/dep-1083-port-flashinfer-stable-va-lifecycle-for-native-all-reduce

* 'main' of https://github.com/NVIDIA/TensorRT-LLM: (83 commits)
  [None][feat] Bind SourceIdentity to checkpoint artifacts (NVIDIA#16159)
  [None][infra] Waive 4 failed cases for main in pre-merge 49550 (NVIDIA#16798)
  [None][fix] Make FlashInfer sampling op wrappers opaque to Dynamo (NVIDIA#16732)
  [None][feat] top-k: route decode to CuTe DSL GVR top-k in e2e (NVIDIA#16420)
  [None][feat] Default GLM-5 to the Python KV-cache transceiver (NVIDIA#16524)
  [None][chore] Add NVTX ranges to per-iteration ADP sync points in PyExecutor (NVIDIA#16422)
  [https://nvbugs/6426850][test] Unwaive Qwen3.5 397B NVFP4 ADP4 TRTLLM test (NVIDIA#16348)
  [https://nvbugs/6445456][fix] Restore inplace ops for functionalization v2 (NVIDIA#16410)
  [None][infra] Waive 1 failed cases for main in pre-merge 49229 (NVIDIA#16786)
  [None][fix] Load DeepSeek V4 mixed-precision NVFP4 checkpoints (NVIDIA#16433)
  [None][feat] ADP conversation router: configurable least-queued placement for new conversations (NVIDIA#16294)
  [None][infra] Waive 1 failed cases for main in pre-merge 49424 (NVIDIA#16780)
  [None][infra] Waive 1 failed cases for main in pre-merge 49424 (NVIDIA#16781)
  [TRTLLMINF-188][infra] Require approval for PerfSanity wildcard runs (NVIDIA#16777)
  [TRTLLM-13969][feat] Support MiniMax M3 for Disaggregated Serving (NVIDIA#16017)
  [NVIDIA#11932][fix] Filter CUTLASS MoE GEMM tile configs by device shared memory on SM121 (NVIDIA#12704)
  [None][chore] Remove attention backend test waivers (NVIDIA#16723)
  [TRTLLM-14540][perf] Skip fp32 state round-trip in FlashInfer GDN pre… (NVIDIA#16703)
  [TRTLLM-13694][feat] Add IBDB recipe provenance and refresh configs (NVIDIA#16254)
  [None][infra] Preview/bump/main (NVIDIA#16758)
  ...

Signed-off-by: Hannah Zhang <hannahz@nvidia.com>
yuanjingx87 pushed a commit to yuanjingx87/TensorRT-LLM that referenced this pull request Jul 26, 2026
NVIDIA#16703)

Signed-off-by: nv-guomingz <137257613+nv-guomingz@users.noreply.github.com>
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