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[None][infra] Waive 1 failed cases for main in pre-merge 49424 - #16781

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dominicshanshan merged 1 commit into
NVIDIA:mainfrom
trtllm-agent:trtllm-ci-report/waive-20260723-061452
Jul 23, 2026
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[None][infra] Waive 1 failed cases for main in pre-merge 49424#16781
dominicshanshan merged 1 commit into
NVIDIA:mainfrom
trtllm-agent:trtllm-ci-report/waive-20260723-061452

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@trtllm-agent trtllm-agent commented Jul 23, 2026

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Auto-generated Waive PR

Created by: TensorRT LLM CI Report (requested by @dominicshanshan)
Target branch: main
Bug(s): 6501404

Waive entries added

unittest/_torch/multi_gpu/test_linear.py::test_row_linear_norm_fusion[2-hidden:16-seqlen:2] SKIP (https://nvbugs/6501404)

This PR was auto-generated by TensorRT LLM CI Report. Please review the waive entries before merging.

Dev Engineer Review

  • Added the requested SKIP waiver for test_row_linear_norm_fusion[2-hidden:16-seqlen:2] under NVBug 6501404.
  • Waiver format and scope are consistent; no public API or code changes.

QA Engineer Review

  • Modified tests/integration/test_lists/waives.txt only; one waiver entry was added.
  • No test code was changed. CBTS coverage data is unavailable.

Verdict: needs follow-up

Bug(s): 6501404
Requested by: @dominicshanshan

Signed-off-by: trtllm-agent <296075020+trtllm-agent@users.noreply.github.com>
@coderabbitai

coderabbitai Bot commented Jul 23, 2026

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Review Change Stack

No actionable comments were generated in the recent review. 🎉

ℹ️ Recent review info
⚙️ Run configuration

Configuration used: Path: .coderabbit.yaml

Review profile: CHILL

Plan: Enterprise

Run ID: b21afd9e-894b-4688-bad1-d251b713b8a1

📥 Commits

Reviewing files that changed from the base of the PR and between 3d86c72 and 65c1f3d.

📒 Files selected for processing (1)
  • tests/integration/test_lists/waives.txt

Walkthrough

Adds a targeted SKIP waiver for the parameterized multi-GPU test_row_linear_norm_fusion case with hidden:16 and seqlen:2, including an NVBug reference.

Changes

Test waiver

Layer / File(s) Summary
Add targeted test waiver
tests/integration/test_lists/waives.txt
Adds a SKIP entry for the specified test_row_linear_norm_fusion parameterization and links the associated NVBug.

Estimated code review effort: 1 (Trivial) | ~2 minutes

Possibly related PRs

Suggested reviewers: qijune, niukuo

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name Status Explanation Resolution
Description check ⚠️ Warning The description has the gist, but it omits the template's Description, Test Coverage, and PR Checklist sections. Add the required Description, Test Coverage, and PR Checklist sections, and briefly state why the waiver is needed and any validation performed.
✅ Passed checks (4 passed)
Check name Status Explanation
Title check ✅ Passed The title matches the change and clearly indicates an infra waiver update for a failed pre-merge case.
Docstring Coverage ✅ Passed No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
✨ Finishing Touches
🧪 Generate unit tests (beta)
  • Create PR with unit tests

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@dominicshanshan

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/bot skip --comment "waive test blocking pre-merge"

@tensorrt-cicd

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PR_Github #61211 [ skip ] triggered by Bot. Commit: 65c1f3d Link to invocation

@tensorrt-cicd

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PR_Github #61211 [ skip ] completed with state SUCCESS. Commit: 65c1f3d
Skipping testing for commit 65c1f3d

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@dominicshanshan
dominicshanshan merged commit c6e0c98 into NVIDIA:main Jul 23, 2026
12 checks passed
hhzhang16 added a commit to hhzhang16/TensorRT-LLM that referenced this pull request Jul 23, 2026
…nnahz/dep-1083-port-flashinfer-stable-va-lifecycle-for-native-all-reduce

* 'main' of https://github.com/NVIDIA/TensorRT-LLM: (83 commits)
  [None][feat] Bind SourceIdentity to checkpoint artifacts (NVIDIA#16159)
  [None][infra] Waive 4 failed cases for main in pre-merge 49550 (NVIDIA#16798)
  [None][fix] Make FlashInfer sampling op wrappers opaque to Dynamo (NVIDIA#16732)
  [None][feat] top-k: route decode to CuTe DSL GVR top-k in e2e (NVIDIA#16420)
  [None][feat] Default GLM-5 to the Python KV-cache transceiver (NVIDIA#16524)
  [None][chore] Add NVTX ranges to per-iteration ADP sync points in PyExecutor (NVIDIA#16422)
  [https://nvbugs/6426850][test] Unwaive Qwen3.5 397B NVFP4 ADP4 TRTLLM test (NVIDIA#16348)
  [https://nvbugs/6445456][fix] Restore inplace ops for functionalization v2 (NVIDIA#16410)
  [None][infra] Waive 1 failed cases for main in pre-merge 49229 (NVIDIA#16786)
  [None][fix] Load DeepSeek V4 mixed-precision NVFP4 checkpoints (NVIDIA#16433)
  [None][feat] ADP conversation router: configurable least-queued placement for new conversations (NVIDIA#16294)
  [None][infra] Waive 1 failed cases for main in pre-merge 49424 (NVIDIA#16780)
  [None][infra] Waive 1 failed cases for main in pre-merge 49424 (NVIDIA#16781)
  [TRTLLMINF-188][infra] Require approval for PerfSanity wildcard runs (NVIDIA#16777)
  [TRTLLM-13969][feat] Support MiniMax M3 for Disaggregated Serving (NVIDIA#16017)
  [NVIDIA#11932][fix] Filter CUTLASS MoE GEMM tile configs by device shared memory on SM121 (NVIDIA#12704)
  [None][chore] Remove attention backend test waivers (NVIDIA#16723)
  [TRTLLM-14540][perf] Skip fp32 state round-trip in FlashInfer GDN pre… (NVIDIA#16703)
  [TRTLLM-13694][feat] Add IBDB recipe provenance and refresh configs (NVIDIA#16254)
  [None][infra] Preview/bump/main (NVIDIA#16758)
  ...

Signed-off-by: Hannah Zhang <hannahz@nvidia.com>
yuanjingx87 pushed a commit to yuanjingx87/TensorRT-LLM that referenced this pull request Jul 26, 2026
…A#16781)

Signed-off-by: trtllm-agent <296075020+trtllm-agent@users.noreply.github.com>
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4 participants